LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 155

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based
PFU-based Distributed Dual Port RAM is also created using the 4-input LUT (Look-Up Table) available in the PFU.
These LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-34. Distributed Dual Port RAM Module Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional such as Clock and Reset is
generated by utilizing the resources available in the PFU.
The various ports and their definitions are listed in Table 9-16. The table lists the corresponding ports for the mod-
ule generated by IPexpress and for the primitive.
Table 9-16. PFU based Distributed Dual-Port RAM Port Definitions
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
Users have the option of enabling the output registers for Distributed Dual Port RAM (Distributed_DPRAM). Fig-
ures 9-35 and 9-36 show the internal timing waveforms for the Distributed Dual Port RAM (Distributed_DPRAM)
with these options.
Generated Module
Port Name in
WrAddress
RdAddress
RdClockEn
WrClockEn
RdClock
WrClock
Data
WE
Q
RdClockEn
WrClockEn
WrAddress
RdAddress
EBR Block Primitive
RdClock
WrClock
Port Name in the
Reset
Data
WE
WAD[3:0]
RDO[1:0]
RAD[3:0]
DI[1:0]
WCK
WRE
—
—
—
Distributed Dual Port
PFU-based
Memory
9-32
Memory Usage Guide for MachXO Devices
Read Clock Enable
Write Clock Enable
Write Address
Read Address
Write Enable
Description
Read Clock
Write Clock
Data Input
Data Out
Q
Rising Clock Edge
Rising Clock Edge
Active State
Active High
Active High
Active High
—
—
—
—