LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 214

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
However, the use of If-Then-Else construct could be a key pitfall to make the design more complex than necessary,
because extra logic are needed to build a priority tree. Consider the following examples:
If the decode conditions are not mutually exclusive, IF-THEN-ELSE construct will cause the last output to be
dependent on all the control signals. The equation for O3 output in example A is:
If the same code can be written as in example B, most of the synthesis tools will remove the priority tree and
decode the output as:
This reduces the logic requirement for the state machine decoder. If each output is indeed dependent of all of the
inputs, it is better to use a CASE statement since CASE statements provide equal branches for each output.
Avoiding Non-intentional Latches
Synthesis tools infer latches from incomplete conditional expressions, such as an IF-THEN-ELSE statements with-
out an Else clause. To avoid non-intentional latches, one should specify all conditions explicitly or specify a default
assignment. Otherwise, latches will be inserted into the resulting RTL code, requiring additional resources in the
device or introducing combinatorial feedback loops that create asynchronous timing problems. Non-intentional
latches can be avoided by using clocked registers or by employing any of the following coding techniques:
Another way to avoid non-intentional latches is to check the synthesis tool outputs. Most of the synthesis tools give
warnings whenever there are latches in the design. Checking the warning list after synthesis will save a tremen-
dous amount of effort in trying to determine why a design is so large later in the Place and Route stage.
HDL Design with Lattice Semiconductor FPGA Devices
The following section discusses the HDL coding techniques utilizing specific Lattice Semiconductor FPGA system
features. This kind of architecture-specific coding style will further improve resource utilization and enhance the
performance of designs.
Lattice Semiconductor FPGA Synthesis Library
The Lattice Semiconductor FPGA Synthesis Library includes a number of library elements to perform specific logic
functions. These library elements are optimized for Lattice Semiconductor FPGAs and have high performance and
utilization. The following are the classifications of the library elements in the Lattice Semiconductor FPGA Synthe-
• Assigning a default value at the beginning of a process
• Assigning outputs for all input conditions
• Using else, (when others) as the final clause
O3 <= z and (s3) and (not (s1 and s2));
O3 <= z and s3;
--A: If-Then-Elese Statement: Complex O3 Equations
process(s1, s2, s3, x, y, z)
begin
end process;
O1 <= ‘0’;
O2 <= ‘0’;
O3 <= ‘0’;
if s1 = ‘1’ then
elsif s2 = ‘1’ then
elsif s3 = ‘1’ then
end if;
O1 <= x;
O2 <= y;
O3 <= z;
13-8
--B: If-Then-Else Statement: Simplified O3 Equation
process (s1, s2, s3, x, y, z)
begin
end process;
O1 <= ‘0’;
O2 <= ‘0’;
O3 <= ‘0’;
if s1 = ‘1’ then
end if;
if s2 = ‘1’ then
end if;
if s3 <= ‘1’ then
end if;
HDL Synthesis Coding Guidelines
O1 <= x;
O2 <= y;
O3 <= z;
for Lattice Semiconductor FPGAs