LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 148

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Figure 9-26. ROM Timing Waveform – without Output Registers
Figure 9-27. ROM Timing Waveform – with Output Registers
First In First Out (FIFO, FIFO_DC) - EBR Based
The EBR blocks in MachXO devices can be configured as Dual Clock First In First Out Memories, FIFO_DC. IPex-
press allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size, according to
design requirements.
IPexpress generates the FIFO_DC memory module as shown in Figure 9-28.
Figure 9-28. FIFO Module Generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For the memory sizes smaller than an EBR
block, the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple
EBR blocks can be cascaded, in depth or width (as required to create these sizes).
OutClockEn
OutClockEn
OutClock
OutClock
Address
Address
Reset
Q
Q
t
t
SUADDR_EBR
SUADDR_EBR
t
t
SUCE_EBR
SUCE_EBR
Invalid Data
RST
CLK
WE
RE
Invalid Data
Add_0
Add_0
DI
t
t
HADDR_EBR
HADDR_EBR
EBR-based First-In First-Out
Add_1
Data_0
Add_1
Memory
9-25
FIFO
Data_0
Data_1
Add_2
Memory Usage Guide for MachXO Devices
Add_2
t
COO_EBR
t
CO_EBR
Data_1
Data_2
Add_3
Add_3
DO
FF
AF
EF
AE
Data_2
Data_3
Add_4
Add_4
t
t
HCE_EBR
HCE_EBR
Data_3
Data_4