LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 145

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Diamond or ispLEVER software automatically generates the additional address decoding logic, which is imple-
mented in the PFU external to the EBR blocks.
Each EBR block consists of 9,216 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block
for the devices are as per Table 9-8.
Table 9-8. MachXO Pseudo-Dual Port Memory Sizes for 9K Memory
Table 9-9 shows the various attributes available for the Pseudo-Dual Port Memory (RAM_DP). Some of these attri-
butes are user-selectable through the IPexpress GUI. For detailed attribute definitions, refer to Appendix A.
Table 9-9. MachXO Pseudo-Dual Port RAM Attributes
Users have the option of enabling the output registers for Pseudo-Dual Port RAM (RAM_DP). Figures 9-23 and 9-
24 show the internal timing waveforms for Pseudo-Dual Port RAM (RAM_DP) with these options.
DATA_WIDTH_W
DATA_WIDTH_R
REGMODE
RESETMODE
CSDECODE_W
CSDECODE_R
ENABLE GSR
Pseudo-Dual
Port Memory
512 x 18
256 x 36
Attribute
8K x 1
4K x 2
2K x 4
1K x 9
Size
Input Data Port
Write Data Word Width
Read Data Word Width
Register Mode (Pipelining)
Selects the Reset type
Chip Select Decode for Write
Chip Select Decode for Read
Enables Global Set Reset
DIA[17:0]
DIA[35:0]
DIA[1:0]
DIA[3:0]
DIA[8:0]
DIA
A
Description
Input Data Port
DIB[17:0]
DIB[35:0]
DIB[1:0]
DIB[3:0]
DIB[8:0]
DIB
B
1, 2, 4, 9, 18, 36
1, 2, 4, 9, 18, 36
NOREG, OUTREG
ASYNC, SYNC
0b000, 0b001, 0b010, 0b011,
0b100, 0b101, 0b110, 0b111
0b000, 0b001, 0b010, 0b011,
0b100, 0b101, 0b110, 0b111
ENABLE, DISABLE
Output Data
DOA[17:0]
DOA[35:0]
DOA[1:0]
DOA[3:0]
DOA[8:0]
Port A
DOA
9-22
Values
Memory Usage Guide for MachXO Devices
Output Data
DOB[17:0]
DOB[35:0]
DOB[1:0]
DOB[3:0]
DOB[8:0]
Port B
DOB
ENABLED
Default
NOREG
ASYNC
Value
0b000
0b000
18
18
Read Address
[MSB:LSB]
RAD[12:0]
RAD[11:0]
RAD[10:0]
RAD[9:0]
RAD[8:0]
RAD[7:0]
Port A
User Selectable through
IPexpress
Write Address
YES
YES
YES
YES
YES
NO
NO
[MSB:LSB]
WAD[12:0]
WAD[11:0]
WAD[10:0]
WAD[9:0]
WAD[8:0]
WAD[7:0]
Port B