LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 150

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Table 9-13. FIFO and FIFO_DC Attributes for MachXO
FIFO_DC Flags
The FIFO_DC have four flags available: Empty, Almost Empty, Almost Full and Full. Almost Empty and Almost Full
flags have a programmable range.
The program ranges for the four FIFO_DC flags are specified in Table 9-14.
Table 9-14. FIFO_DC Flag Settings
The only restriction on the flag setting is that the values must be in a specific order (Empty=0, Almost Empty next,
followed by Almost Full and Full, respectively). The value of Empty is not equal to the value of Almost Empty (or
Full is equal to Almost Full). In this case, a warning is generated and the value of Empty (or Full) is used in place of
Almost Empty (or Almost Full). When coming out of reset, the active high flags Empty and Almost Empty are set to
high, since they are true.
The user should specify the absolute value of the address at which the Almost Empty and Almost Full flags will go
true. For example, if the Almost Full flag is required to go true at the address location 500 for a FIFO of depth 512,
the user should specify a value of 500 in IPexpress.
The Empty and Almost Empty flags are always registered to the read clock and the Full and Almost Full flags are
always registered to the write clock.
At reset both the write and read counters are pointing to address zero. After reset is de-asserted data can be writ-
ten into the FIFO_DC to the address pointed to by the write counter at the positive edge of the write clock when the
write enable is asserted.
DATA_WIDTH_W
DATA_WIDTH_R
REGMODE
RESETMODE
CSDECODE_W
CSDECODE_R
GSR
AEPOINTER
AFPOINTER
FULLPOINTER
FULLPOINTER1
AFPOINTER1
AEPOINTER1
FIFO Attribute Name
Attribute
AFF
AEF
FF
EF
Data Width Write Mode
Data Width Read Mode
Register Mode
Select Reset Type
Chip Select Decode for Write Mode
Chip Select Decode for Read Mode
Enable Global Set Reset
Almost Empty Pointer
Almost Full Pointer
Full Pointer
Full Pointer1
Almost Full Pointer1
Almost Empty Pointer1
Almost empty setting
Almost full setting
Full flag setting
Empty setting
Description
Description
9-27
Programming Range
Memory Usage Guide for MachXO Devices
1 to (FF-1)
1 to (FF-1)
1, 2, 4, 9, 18, 36
1, 2, 4, 9, 18, 36
NOREG, OUTREG
ASYNC, SYNC
0b00, 0b01, 0b10, 0b11
0b00, 0b01, 0b10, 0b11
ENABLED, DISABLED
Ob00000000000000, .....,
0b11111111111111
Ob00000000000000, .....,
0b11111111111111
Ob00000000000000, .....,
0b11111111111111
Ob00000000000000, .....,
0b11111111111111
Ob00000000000000, .....,
0b11111111111111
Ob00000000000000, .....,
0b11111111111111
2
N
0
- 1
Values
Program Bits
14
14
14
5
ENABLED
NOREG
ASYNC
Default
Value
18
18
—
—
—
—
—
—
0
0