LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 125

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Memory Usage Guide for MachXO Devices
The PFU contains the building blocks for logic and Distributed RAM and ROM. The PFF provides the logic building
blocks without the distributed RAM This document describes the memory usage and implementation for both
Embedded Memory Blocks (EBRs) and Distributed RAM of the PFU. Refer to the
MachXO Family Data Sheet
for
details on the hardware implementation of the EBR and Distributed RAM.
The logic blocks are arranged in a two-dimensional grid with rows and columns as shown in the figures below. The
physical location of the EBR and Distributed RAM follows the row and column designation. Since the Distributed
RAM is part of the PFU resource, it follows the PFU/PFF row and column designation. The EBR occupies two col-
umns per block to account for the wider port interface.
Utilizing IPexpress
Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules will be con-
structed using one or more memory primitives along with general purpose routing and LUTs as required. The avail-
able primitives are:
• Single Port RAM (RAM_DQ) – EBR-based
• Dual PORT RAM (RAM_DP_TRUE) – EBR-based
• Pseudo Dual Port RAM (RAM_DP) – EBR-based
• Read Only Memory (ROM) – EBR-Based
• First In First Out Memory (Dual Clock) (FIFO_DC) – EBR-based
• Distributed Single Port RAM (Distributed_SPRAM) – PFU-based
• Distributed Dual Port RAM (Distributed_DPRAM) – PFU-based
• Distributed ROM (Distributed_ROM) – PFU/PFF-based
• RAM Based Shift Register (RAM_Based_Shift_Register) – PFU-based
• Distributed Shift Register (RAM_Based_Shift_Register) - PFU based (see IPexpress Help for details)
IPexpress Flow
For generating any of these memories, create (or open) a project for the MachXO devices.
From Diamond or the ispLEVER Project Navigator, select Tools > IPexpress. Alternatively, users can also click on
the button in the toolbar shown below when the MachXO devices are targeted in the project.
This opens the IPexpress window as shown in Figure 9-2.
9-2