LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 124

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

October 2010
Introduction
This technical note discusses memory usage for the Lattice MachXO device family. It is intended to be used by
design engineers as a guide in integrating the EBR and PFU based memories for these device families in isp-
LEVER
The architecture of these devices provides resources for memory intensive applications. The sysMEM™ Embed-
ded Block RAM (EBR) complements its distributed PFU-based memory. Single-Port RAM, Dual-Port RAM, Pseudo
Dual-Port RAM, FIFO and ROM memories can be constructed using the EBR. LUTs and PFU can implement Dis-
tributed Single-Port RAM, Dual-Port RAM and ROM.
The capabilities of the EBR Block RAM and PFU RAM are referred to as primitives and are described later in this
document. Designers can utilize the memory primitives in two ways:
• Via IPexpress™ – The IPexpress GUI allows users to specify the memory type and size that is required. IPex-
• Via the PMI (Parameterizable Module Inferencing) – PMI allows experienced users to skip the graphical inter-
The remainder of this document discusses these approaches, utilizing IPexpress, PMI inference, memory modules
and memory primitives.
MachXO Device Memories
Only the MachXO1200 and MachXO2280 devices contain the sysMEM EBR blocks along with an array of logic
blocks called PFUs (or PFFs) surrounded by Programmable I/O Cells (PICs). This is shown in Figure 9-1.
Figure 9-1. Logical View of MachXO1200 and MachXO2280 Devices
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press takes this specification and constructs a netlist to implement the desired memory by using one or more of
the memory primitives.
face and utilize the configurable memory modules on the fly from the ispLEVER Project Navigator or Diamond.
The parameters and the control signals needed either in Verilog or VHDL can be set. The top-level design will
have the parameters defined and signals declared so the interface can automatically generate the black box dur-
ing synthesis.
®
and Lattice Diamond™ design software.
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCLOCK PLL
Programmable Functional Unit (PFUs) with RAM
9-1
Memory Usage Guide for
PIOs Arranged into
sysIO Banks
Programmable
Function Units
(PFFs) without
RAM
MachXO Devices
Technical Note TN1092
tn1092_01.5