LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 144

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Pseudo Dual Port RAM (RAM_DP)- EBR Based
The EBR blocks in the MachXO devices can be configured as Pseudo-Dual Port RAM or RAM_DP. IPexpress
allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size as per design require-
ments.
IPexpress generates the memory module as shown in Figure 9-22.
Figure 9-22. Pseudo Dual Port Memory Module Generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For the memory sizes smaller than an EBR
block, the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple
EBR blocks can be cascaded in depth or width (as required to create these sizes).
In Pseudo Dual Port RAM mode, the input data and address for the ports are registered at the input of the memory
array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for the Single Port Memory are listed in Table 9-7. The table lists the corre-
sponding ports for the module generated by IPexpress and for the EBR RAM_DP primitive.
Table 9-7. EBR-Based Pseudo-Dual Port Memory Port Definitions
Reset (RST) resets only the input and output registers of the RAM. It does not reset the contents of the memory.
Chip Select (CS) is a useful port when multiple cascaded EBR blocks are required by the memory. The CS signal
forms the MSB for the address when multiple EBR blocks are cascaded. Since CS is a 3-bit bus, it can cascade
eight memories easily. However, if the memory size specified by the user requires more than eight EBR blocks, the
Generated Module
Port Name in
RdAddress
WrAddress
RdClockEn
WrClockEn
RdClock
WrClock
Reset
Data
WE
—
Q
WrClockEn
WrAddress
Port Name in the EBR
WrClock
Reset
Block Primitive
Data
WE
ADW[x2:0]
ADR[x1:0]
DO[y1:0]
DI[y2:0]
CS[2:0]
CLKW
CLKR
CEW
CER
RST
WE
Pseudo Dual
Port Memory
EBR-based
RAM_DP
9-21
Memory Usage Guide for MachXO Devices
Read Clock Enable
Write Clock Enable
Read Address
Write Address
Write Enable
Description
Read Clock
Write Clock
Chip Select
Read Data
Write Data
Reset
RdClock
RdClockEn
RdAddress
Q
Rising Clock Edge
Rising Clock Edge
Active State
Active High
Active High
Active High
Active High
—
—
—
—
—