LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 4

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Memory Usage Guide for MachXO Devices
Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based 32
MachXO sysCLOCK Design and Usage Guide
Design Considerations and Usage................................................................................................................... 8-10
Technical Support Assistance.......................................................................................................................... 8-11
Revision History ............................................................................................................................................... 8-12
Appendix A. HDL Attributes for Synplify
Appendix B. sysIO Attributes Using the ispLEVER Preference Editor or 
Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-19
Introduction ........................................................................................................................................................ 9-1
MachXO Device Memories ................................................................................................................................ 9-1
Utilizing IPexpress.............................................................................................................................................. 9-2
Initializing Memory ........................................................................................................................................... 9-36
Technical Support Assistance.......................................................................................................................... 9-37
Revision History ............................................................................................................................................... 9-38
Appendix A. Attribute Definitions...................................................................................................................... 9-39
Introduction ...................................................................................................................................................... 10-1
MachXO Top Level View.................................................................................................................................. 10-1
sysCLOCK PLL ................................................................................................................................................ 10-1
Features ........................................................................................................................................................... 10-2
Functional Description...................................................................................................................................... 10-2
MachXO PLL Primitive Definitions ................................................................................................................... 10-4
PLL Attributes Definitions................................................................................................................................. 10-5
MachXO PLL Usage in IPexpress.................................................................................................................... 10-8
Oscillator (OSCC) .......................................................................................................................................... 10-13
Clock/Control Distribution Network ................................................................................................................ 10-13
Diamond Spreadsheet View ....................................................................................................................... 8-17
LOC......................................................................................................................................................... 8-10
Banking Rules ......................................................................................................................................... 8-10
Zero Hold Time ....................................................................................................................................... 8-10
Fast Output Path ..................................................................................................................................... 8-10
Dedicated Pins ........................................................................................................................................ 8-10
Differential I/O Implementation................................................................................................................ 8-11
VHDL Synplify/Precision RTL Synthesis................................................................................................. 8-13
Verilog Synpilfy ....................................................................................................................................... 8-15
Verilog Precision RTL Synthesis............................................................................................................. 8-16
IOBUF ..................................................................................................................................................... 8-19
LOCATE.................................................................................................................................................. 8-19
IPexpress Flow.......................................................................................................................................... 9-2
True Dual Port RAM (RAM_DP_TRUE) – EBR Based ........................................................................... 9-12
Pseudo Dual Port RAM (RAM_DP)- EBR Based.................................................................................... 9-21
Read Only Memory (ROM) – EBR Based............................................................................................... 9-23
First In First Out (FIFO, FIFO_DC) - EBR Based.................................................................................... 9-25
Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 9-30
Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 9-35
Initialization File Formats ........................................................................................................................ 9-36
PLL Divider and Delay Blocks................................................................................................................. 10-2
PLL Inputs and Outputs .......................................................................................................................... 10-3
Dynamic Delay Control I/O Ports ............................................................................................................ 10-3
PLL Attributes.......................................................................................................................................... 10-4
Dynamic Delay Adjustment ..................................................................................................................... 10-7
Configuration Tab.................................................................................................................................... 10-9
Mode ....................................................................................................................................................... 10-9
Frequency Programming in Divider Mode for Advanced Users ............................................................ 10-11
®
and Precision
3
®
RTL Synthesis ........................................................ 8-13
MachXO Family Handbook
Table of Contents