LCMXO2280C-5TN144C LATTICE SEMICONDUCTOR, LCMXO2280C-5TN144C Datasheet - Page 168

• Manufacturer Part Number: LCMXO2280C-5TN144C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, SMD
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO2280C-5TN144C

• Cpld Type: FLASH
• No. Of Macrocells: 1140
• No. Of I/o's: 113
• Propagation Delay: 3.6ns
• Global Clock Setup Time: 1.1ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Table 10-3. MachXO PLL User Attributes (Continued)
FDEL Settings
There are four ways the user can enter the desired FDEL value.
Duty Cycle Selection 
(1/8 Increment)
Delay Control
Feedback Mode
CLKOS Select
CLKOK Select
1. DYNAMIC This mode switches delay control between Dynamic and Static depending upon the input logic of DDAMODE pin.
2. CLKOP_DIV value is calculated to maximize the f
3. The CLKOP Divider values are 2, 4, 6, 8,…30, 32 if CLKOS is unused and 2, 4, 8, 16, 32 if CLKOS is used.
4. All divider settings are user transparent in Frequency Mode. These are user attributes in Divider Mode.
5. CLKFB source:
6. Refer to the
7. This attribute is not available in the IPexpress GUI. After reviewing the trace report file, users can determine the amount of delay that will
STATIC
CLKI_DIV and CLKFB_DIV values.
INTERNAL: CLKINTFB (internal feedback path is used).
CLKOP: Primary Clock net feedback node of CLKOP.
User Clock:
- General routing (includes FPGA logic or general I/O)
- Primary Clock net (includes user connecting CLKOP to CLKFB internally to the chip, or the use of a device clock pin)
- Dedicated PLL feedback pin
best fit the clocking in their design. Further information on FDEL settings is described in the following section.
1. Although the FDEL entry is not available in the IPexpress GUI, the module generated by IPexpress
2. Preference File: User may specify the preference in the Preference file.
3. Pre-Map Preference Editor: Users can enter the FDEL value in the Pre-Map Preference Editor as shown in
Attributes
includes the attribute with default value “0”. Users can replace it with a desired value.

Example of source code with default FDEL value:

Example:
Figure 10-5. Figure 10-5 shows the Pre-Map Preference Editor in the ispLEVER software. To see a similar
screen shot for Lattice Diamond™ software, go to Appendix A, Figure 10-16.
This mode sets the delay control to Static Control.
MachXO Family Data Sheet
attribute FDEL of ehxpll_mod_0_0 : label is "0";
generic map (…
ASIC "FDEL_CODE_0_0" TYPE "EHXPLLB" FDEL="-2"
FDEL=>"0",
…
")
MM GUI
Access
Y
Y
Y
Y
Y
for current specifications.
Attribute Name
DELAY_CNTL
VCO
Note 5
DUTY
within the specified range based on FIN, CLKOP_FREQ in conjunction with
1
10-6
Preference
Support
Editor
N
N
N
N
N
INTERNAL/CLKOP/UserClock
;
DYNAMIC/STATIC
Design and Usage Guide
MachXO sysCLOCK PLL
Value
1 to 7
Default
CLKOP
STATIC
Value
4