MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 107

MC68376BAMFT20

Manufacturer Part Number
MC68376BAMFT20
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68376BAMFT20

Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Interface Type
QSPI/SCI
Program Memory Type
ROM
Program Memory Size
8KB
Total Internal Ram Size
7.5KB
# I/os (max)
18
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
On-chip Adc
16-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
160
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68376BAMFT20
Manufacturer:
FREESCAL
Quantity:
245
5.6.2.2 Write Cycle
MC68336/376
USER’S MANUAL
During a write cycle, the MCU transfers data to an external memory or peripheral de-
vice. If the instruction specifies a long-word or word operation, the MCU attempts to
write two bytes at once. For a byte operation, the MCU writes one byte. The portion of
the data bus upon which each byte is written depends on operand size, peripheral ad-
dress, and peripheral port size.
Refer to 5.5.2 Dynamic Bus Sizing and 5.5.4 Misaligned Operands for more infor-
mation. Figure 5-11 is a flowchart of a write-cycle operation for a word transfer. Refer
to the SIM Reference Manual (SIMRM/AD) for more information.
1) NEGATE DS AND AS
2) REMOVE DATA FROM DATA BUS
1) SET R/W TO WRITE
2) DRIVE ADDRESS ON ADDR[23:0]
3) DRIVE FUNCTION CODE ON FC[2:0]
4) DRIVE SIZ[1:0] FOR OPERAND SIZE
ASSERT DS AND WAIT FOR DSACK (S3)
TERMINATE OUTPUT TRANSFER (S5)
PLACE DATA ON DATA[15:0] (S2)
OPTIONAL STATE (S4)
ADDRESS DEVICE (S0)
START NEXT CYCLE
ASSERT AS (S1)
NO CHANGE
MCU
Figure 5-11 Write Cycle Flowchart
SYSTEM INTEGRATION MODULE
1) DECODE ADDRESS
2) LATCH DATA FROM DATA BUS
3) ASSERT DSACK SIGNALS
ACCEPT DATA (S2 + S3)
TERMINATE CYCLE
NEGATE DSACK
PERIPHERAL
MOTOROLA
WR CYC FLOW
5-29

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