MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 377

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

DIV23 — Divide By 2/Divide By 3
PSEL[1:0] — Prescaler Division Ratio Select
D.7.5 CPSM Test Register
CPTR — CPSM Test Register
D.7.6 FCSM Status/Interrupt/Control Register
FCSMSIC — FCSM Status/Interrupt/Control Register
COF — Counter Overflow Flag
MC68336/376
USER’S MANUAL
COF
15
U
RESET:
The DIV23 bit is a read/write control bit that selects the division ratio of the first pres-
caler stage. It may be changed at any time.
This bit field selects the division ratio of the programmable prescaler output signal
PCLK6. Refer to Table D-38.
Used only during factory test.
This flag indicates whether or not a counter overflow has occurred. An overflow is de-
fined as the transition of the counter from $FFFF to $0000. If the IL[2:0] field is non-
zero, an interrupt request is generated when the COF bit is set.
This flag bit is set only by hardware and cleared by software or system reset. To clear
the flag, first read the bit as a one, then write a zero to the bit.
0 = First prescaler stage divides by two.
1 = First prescaler stage divides by three.
0 = Counter overflow has not occurred
1 = Counter overflow has occurred
14
0
IL[2:0]
13
0
DIV23
Prescaler Control Bits
0
0
0
0
1
1
1
1
Table D-38 Prescaler Division Ratio Select Field
12
0
PSEL1 PSEL0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6
0
0
1
1
0
0
1
1
IARB3
11
0
USED
NOT
10
0
1
0
1
0
1
0
1
DRVA
REGISTER SUMMARY
9
0
2
2
2
2
3
3
3
3
DRVB
8
0
4
4
4
4
6
6
6
6
Prescaler Division Ratio
IN
U
7
12
12
12
12
8
8
8
8
6
16
16
16
16
24
24
24
24
NOT USED
5
4
32
32
32
32
48
48
48
48
3
128
256
512
192
384
768
64
96
2
0
$YFF40A
MOTOROLA
$YFF460
CLK[2:0]
1
0
D-59
0
0