MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 130

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

5.8.3 Interrupt Acknowledge and Arbitration
5-52
MOTOROLA
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt
source of higher priority makes a service request while a lower priority request is pend-
ing, the higher priority request is serviced. If an interrupt request with a priority equal
to or lower than the current IP mask value is made, the CPU32 does not recognize the
occurrence of the request. If simultaneous interrupt requests of different priorities are
made, and both have a priority greater than the mask value, the CPU32 recognizes
the higher-level request.
When the CPU32 detects one or more interrupt requests of a priority higher than the
interrupt priority mask value, it places the interrupt request level on the address bus
and initiates a CPU space read cycle. The request level serves two purposes: it is de-
coded by modules or external devices that have requested interrupt service, to deter-
mine whether the current interrupt acknowledge cycle pertains to them, and it is
latched into the interrupt priority mask field in the CPU32 status register to preclude
further interrupts of lower priority during interrupt service.
Modules or external devices that have requested interrupt service must decode the IP
mask value placed on the address bus during the interrupt acknowledge cycle and re-
spond if the priority of the service request corresponds to the mask value. However,
before modules or external devices respond, interrupt arbitration takes place.
Arbitration is performed by means of serial contention between values stored in indi-
vidual module interrupt arbitration (IARB) fields. Each module that can make an inter-
rupt service request, including the SIM, has an IARB field in its configuration register.
IARB fields can be assigned values from %0000 to %1111. In order to implement an
arbitration scheme, each module that can request interrupt service must be assigned
a unique, non-zero IARB field value during system initialization. Arbitration priorities
range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an interrupt
service request from a source that has an IARB field value of %0000, a spurious inter-
rupt exception is processed.
Because the EBI manages external interrupt requests, the SIM IARB value is used for
arbitration between internal and external interrupt requests. The reset value of IARB
for the SIM is %1111, and the reset IARB value for all other modules is %0000.
Although arbitration is intended to deal with simultaneous requests of the same
interrupt level, it always takes place, even when a single source is requesting service.
This is important for two reasons: the EBI does not transfer the interrupt acknowledge
read cycle to the external bus unless the SIM wins contention, and failure to contend
causes the interrupt acknowledge bus cycle to be terminated early by a bus error.
Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same nonzero value, the
CPU32 interprets multiple vector numbers at the same time, with un-
predictable consequences.
SYSTEM INTEGRATION MODULE
WARNING
USER’S MANUAL
MC68336/376