MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 152

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

9.2 QSM Registers and Address Map
9.2.1 QSM Global Registers
9.2.1.1 Low-Power Stop Operation
9-2
MOTOROLA
The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates
in either full- or half-duplex mode. There are separate transmitter and receiver enable
bits and dual data buffers. A modulus-type baud rate generator provides rates from
110 baud to 655 kbaud with a 20.97 MHz system clock. Word length of either eight or
nine bits is software selectable. Optional parity generation and detection provide either
even or odd parity check capability. Advanced error detection circuitry catches glitches
of up to 1/16 of a bit time in duration. Wake-up functions allow the CPU32 to run unin-
terrupted until meaningful data is available.
There are four types of QSM registers: QSM global registers, QSM pin control regis-
ters, QSPI registers, and SCI registers. Refer to 9.2.1 QSM Global Registers and
9.2.2 QSM Pin Control Registers for a discussion of global and pin control registers.
Refer to 9.3.1 QSPI Registers and 9.4.1 SCI Registers for further information about
QSPI and SCI registers. Writes to unimplemented register bits have no effect, and
reads of unimplemented bits always return zero.
The QSM address map includes the QSM registers and the QSPI RAM. The MM bit in
the system integration module configuration register (SIMCR) defines the most signif-
icant bit (ADDR23) of the IMB address for each module.
Refer to D.6 Queued Serial Module for a QSM address map and register bit and field
definitions. 5.2.1 Module Mapping contains more information about how the state of
MM affects the system.
The QSM configuration register (QSMCR) contains parameters for interfacing to the
CPU32 and the intermodule bus. The QSM test register (QTEST) is used during fac-
tory test of the QSM. The QSM interrupt level register (QILR) determines the priority
of interrupts requested by the QSM and the vector used when an interrupt is acknowl-
edged. The QSM interrupt vector register (QIVR) contains the interrupt vector for both
QSM submodules. QILR and QIVR are 8-bit registers located at the same word ad-
dress.
When the STOP bit in QSMCR is set, the system clock input to the QSM is disabled
and the module enters a low-power operating state. QSMCR is the only register guar-
anteed to be readable while STOP is asserted. The QSPI RAM is not readable during
LPSTOP. However, writes to RAM or any register are guaranteed valid while STOP is
asserted. STOP can be set by the CPU32 and by reset.
System software must bring the QSPI and SCI to an orderly stop before asserting
STOP to avoid data corruption. The IRQ mask level in the CPU32 status register
should be set to a higher value than the IRQ level generated by the QSM module. The
SCI receiver and transmitter should be disabled after transfers in progress are com-
plete. The QSPI can be halted by setting the HALT bit in SPCR3 and then setting
STOP after the HALTA flag is set. The IRQ mask in the CPU status register should be
restored to its former level. Refer to 5.3.4 Low-Power Operation for more information
about low-power stop mode.
QUEUED SERIAL MODULE
USER’S MANUAL
MC68336/376