MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 141

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

MC68336/376
USER’S MANUAL
Following reset, the MCU fetches the initial stack pointer and program counter values
from the exception vector table, beginning at $000000 in supervisor program space.
The CSBOOT chip-select signal is used to select an external boot device mapped to
a base address of $000000.
The MSB of the CSBTPA field in CSPAR0 has a reset value of one, so that chip-select
function is selected by default out of reset. The BYTE field in chip-select option register
CSORBT has a reset value of “both bytes” so that the select signal is enabled out of
reset. The LSB of the CSBOOT field, determined by the logic level of DATA0 during
reset, selects the boot ROM port size. When DATA0 is held low during reset, port size
is eight bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a
weak internal pull-up driver, so that a 16-bit port is selected by default out of reset.
However, the internal pull-up driver can be overcome by bus loading effects. To en-
sure a particular configuration out of reset, use an active device to put DATA0 in a
known state during reset.
The base address field in the boot chip-select base address register CSBARBT has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of one Mbyte. Table 5-22 shows CSBOOT reset values.
Table 5-22 CSBOOT Base and Option Register Reset Values
Table 5-21 Chip-Select Base and Option Register Reset Values
NOTES:
Async/sync mode
Upper/lower byte
1. These fields are not used unless “Address space” is set to CPU space.
Address space
Base address
Read/write
Autovector
Block size
DSACK
AS/DS
Fields
IPL
1
Async/sync mode
Upper/lower byte
Address space
Base address
Read/write
Autovector
Block size
SYSTEM INTEGRATION MODULE
DSACK
AS/DS
Fields
IPL
Interrupt vector externally
Supervisor/user space
Asynchronous mode
External interrupt vector
Asynchronous mode
Reset Values
13 wait states
Both bytes
Read/write
No wait states
Any level
Reset Values
$000000
1 Mbyte
CPU space
Any level
$000000
Disabled
Disabled
AS
2 Kbyte
AS
MOTOROLA
5-63