MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 8

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Paragraph
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.8
8.8.1
8.8.2
8.9
8.10
8.11
8.11.1
8.11.1.1
8.11.2
8.11.3
8.11.4
8.11.5
8.12
8.12.1
8.12.2
8.12.3
8.12.3.1
8.12.3.2
8.12.3.3
8.12.4
8.12.5
8.12.6
8.12.6.1
8.12.6.2
8.12.6.3
8.12.6.4
8.12.7
8.12.8
8.13
8.13.1
8.13.2
8.13.3
8.13.4
viii
MOTOROLA
QADC Bus Interface .................................................................................. 8-6
Module Configuration ................................................................................ 8-6
Test Register ............................................................................................. 8-8
General-Purpose I/O Port Operation ......................................................... 8-8
External Multiplexing Operation .............................................................. 8-10
Analog Input Channels ............................................................................ 8-12
Analog Subsystem .................................................................................. 8-12
Digital Control Subsystem ....................................................................... 8-16
Interrupts ................................................................................................. 8-32
Low-Power Stop Mode ...................................................................... 8-6
Freeze Mode ..................................................................................... 8-7
Supervisor/Unrestricted Address Space ........................................... 8-7
Interrupt Arbitration Priority ............................................................... 8-8
Port Data Register ............................................................................. 8-9
Port Data Direction Register .............................................................. 8-9
Conversion Cycle Times ................................................................. 8-13
Front-End Analog Multiplexer .......................................................... 8-15
Digital to Analog Converter Array .................................................... 8-15
Comparator ..................................................................................... 8-16
Successive Approximation Register ................................................ 8-16
Queue Priority ................................................................................. 8-16
Queue Boundary Conditions ........................................................... 8-19
Scan Modes .................................................................................... 8-20
QADC Clock (QCLK) Generation .................................................... 8-24
Periodic/Interval Timer .................................................................... 8-27
Control and Status Registers .......................................................... 8-28
Conversion Command Word Table ................................................. 8-28
Result Word Table ........................................................................... 8-31
Interrupt Sources ............................................................................. 8-32
Interrupt Register ............................................................................. 8-32
Interrupt Vectors .............................................................................. 8-33
Initializing the QADC for Interrupt Driven Operation ....................... 8-34
Amplifier Bypass Mode Conversion Timing ............................ 8-14
Disabled Mode and Reserved Mode ....................................... 8-20
Single-Scan Modes ................................................................. 8-20
Continuous-Scan Modes ......................................................... 8-22
Control Register 0 (QACR0) ................................................... 8-28
Control Register 1 (QACR1) ................................................... 8-28
Control Register 2 (QACR2) ................................................... 8-28
Status Register (QASR) .......................................................... 8-28
SECTION 9 QUEUED SERIAL MODULE
TABLE OF CONTENTS
(Continued)
Title
USER’S MANUAL
MC68336/376
Page