MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 21

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Table
3-1
3-2
3-3
3-4
3-5
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
6-1
7-1
7-2
8-1
8-2
8-3
8-4
MC68336/376
USER’S MANUAL
MC68336/376 Pin Characteristics................................................................... 3-7
MC68336/376 Output Driver Types................................................................. 3-8
MC68336/376 Power Connections.................................................................. 3-8
MC68336/376 Signal Characteristics .............................................................. 3-9
MC68336/376 Signal Functions .................................................................... 3-11
Unimplemented MC68020 Instructions ......................................................... 4-10
Instruction Set Summary ............................................................................... 4-11
Exception Vector Assignments...................................................................... 4-16
BDM Source Summary.................................................................................. 4-20
Polling the BDM Entry Source....................................................................... 4-21
Background Mode Command Summary ....................................................... 4-22
CPU Generated Message Encoding ............................................................. 4-25
Show Cycle Enable Bits .................................................................................. 5-3
Clock Control Multipliers.................................................................................. 5-8
System Frequencies from 4.194 MHz Reference ......................................... 5-10
Bus Monitor Period........................................................................................ 5-15
MODCLK Pin and SWP Bit During Reset ..................................................... 5-16
Software Watchdog Ratio.............................................................................. 5-16
MODCLK Pin and PTP Bit at Reset .............................................................. 5-17
Periodic Interrupt Priority............................................................................... 5-18
Size Signal Encoding .................................................................................... 5-22
Effect of DSACK Signals ............................................................................... 5-24
Operand Alignment ....................................................................................... 5-26
DSACK, BERR, and HALT Assertion Results............................................... 5-35
Reset Source Summary ................................................................................ 5-41
Reset Mode Selection ................................................................................... 5-42
Module Pin Functions During Reset.............................................................. 5-46
SIM Pin Reset States .................................................................................... 5-47
Chip-Select Pin Functions ............................................................................. 5-57
Pin Assignment Field Encoding..................................................................... 5-58
Block Size Encoding...................................................................................... 5-59
Chip-Select Base and Option Register Reset Values ................................... 5-63
CSBOOT Base and Option Register Reset Values....................................... 5-63
SRAM Array Address Space Type .................................................................. 6-2
ROM Array Space Type .................................................................................. 7-2
Wait States Field ............................................................................................. 7-2
Multiplexed Analog Input Channels................................................................. 8-5
Analog Input Channels .................................................................................. 8-12
Queue 1 Priority Assertion ............................................................................ 8-17
QADC Clock Programmability ....................................................................... 8-27
Address Space Encoding ............................................................................. 5-23
LIST OF TABLES
Title
MOTOROLA
Page
xxi