MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 198

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

8.11.4 Comparator
8.11.5 Successive Approximation Register
8.12 Digital Control Subsystem
8.12.1 Queue Priority
8-16
MOTOROLA
The comparator is used during the approximation process to sense whether the digi-
tally selected arrangement of the DAC array produces a voltage level higher or lower
than the sampled input. The comparator output feeds into the SAR which accumulates
the A/D conversion result sequentially, starting with the MSB.
The input of the successive approximation register (SAR) is connected to the compar-
ator output. The SAR sequentially receives the conversion value one bit at a time,
starting with the MSB. After accumulating the ten bits of the conversion result, the SAR
data is transferred to the appropriate result location, where it may be read by user
software.
The digital control subsystem includes conversion sequencing logic, channel selection
logic, the clock and periodic/interval timer, control and status registers, the conversion
command word table RAM, and the result word table RAM.
The central element for control of the QADC conversions is the 40-entry conversion
command word (CCW) table. Each CCW specifies the conversion of one input chan-
nel. Depending on the application, one or two queues can be established in the CCW
table. A queue is a scan sequence of one or more input channels. By using a pause
mechanism, subqueues can be created in the two queues. Each queue can be oper-
ated using several different scan modes. The scan modes for queue 1 and queue 2
are programmed in QACR1 and QACR2. Once a queue has been started by a trigger
event (any of the ways to cause the QADC to begin executing the CCWs in a queue
or subqueue), the QADC performs a sequence of conversions and places the results
in the result word table.
Queue 1 has execution priority over queue 2 execution. Table 8-3 shows the condi-
tions under which queue 1 asserts its priority:
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
USER’S MANUAL
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