MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 279

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

MC68336/376
USER’S MANUAL
Num
NOTES:
1
2
3
4
5
6
1. All internal registers retain data at 0 Hz.
2. This parameter is periodically sampled rather than 100% tested.
3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
4. Proper layout procedures must be followed to achieve specifications.
5. Assumes that stable V
6. Internal VCO frequency (f
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maxi-
external resistance from the XFC pin due to external leakage must be greater than 15 M
specification. Filter network geometry can vary depending upon operating environment
time V
for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while
the PLL is running, and to the period required for the clock to lock after LPSTOP.
vide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f
f
specified f
mum f
nal clock signal. Noise injected into the PLL circuitry via V
frequency increase the J
operation, this parameter should be measured during functional testing of the final system.
VCO
PLL Reference Frequency Range
System Frequency
PLL Lock Time
VCO Frequency
Limp Mode Clock Frequency
CLKOUT Jitter
On-Chip PLL System Frequency
External Clock Operation
SYNCR X bit = 0
SYNCR X bit = 1
Short term (5 s interval)
Long term (500 s interval)
(V
sys
DD
4. When X = 1, the divider is disabled, and f
DD
. Measurements are made with the device powered by filtered supplies and clocked by a stable exter-
and V
sys
and V
.
DDSYN
2, 3, 4, 7
2, 3, 4, 5
DDSYN
Characteristic
6
1
DDSYN
are valid until RESET is released. This specification also applies to the period required
= 5.0 Vdc
clk
VCO
percentage for a given interval. When jitter is a critical constraint on control system
Table A-4 Clock Control Timing
is applied, and that the crystal oscillator is stable. Lock time is measured from the
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a di-
ELECTRICAL CHARACTERISTICS
5%, V
SS
= 0 Vdc, T
sys
= f
Symbol
VCO
f
f
f
J
t
VCO
f
limp
sys
ref
lpll
clk
A
DDSYN
2. X must equal one when operating at maximum
= T
L
to T
and V
–0.0625
–0.625
4.194
f
ref
H,
Min
dc
dc
—
—
—
—
/32
SS
4.194 MHz reference)
and variation in crystal oscillator
2 (f
f
sys
–0.0625
f
–0.625
sys
5.243
20.97
20.97
20.97
sys
.
Max
20
max/2
max
max)
to guarantee this
MOTOROLA
MHz
MHz
MHz
MHz
Unit
ms
%
sys
A-3
=