MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 92

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

5.4 System Protection
5.4.1 Reset Status
5.4.2 Bus Monitor
5-14
MOTOROLA
The system protection block preserves reset status, monitors internal activity, and pro-
vides periodic interrupt generation. Figure 5-6 is a block diagram of the submodule.
The reset status register (RSR) latches internal MCU status during reset. Refer to
5.7.10 Reset Status Register for more information.
The internal bus monitor checks data and size acknowledge (DSACK) or autovector
(AVEC) signal response times during normal bus cycles. The monitor asserts the in-
ternal bus error (BERR) signal when the response time is excessively long.
DSACK and AVEC response times are measured in clock cycles. Maximum allowable
response time can be selected by setting the bus monitor timing (BMT[1:0]) field in the
system protection control register (SYPCR). Table 5-4 shows the periods allowed.
CLOCK
2
9
PRESCALER
Figure 5-6 System Protection Block
SYSTEM INTEGRATION MODULE
SPURIOUS INTERRUPT MONITOR
MODULE CONFIGURATION
RESET STATUS
HALT MONITOR
BUS MONITOR
AND TEST
SOFTWARE WATCHDOG TIMER
PERIODIC INTERRUPT TIMER
RESET REQUEST
BERR
RESET REQUEST
IRQ[7:1]
USER’S MANUAL
MC68336/376
SYS PROTECT BLOCK