MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 348

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

PORTQA — Port QA Data Register
PORTQB — Port QB Data Register
DDRQA — Port QA Data Direction Register
IVB[7:0] — Interrupt Vector Base
D.5.4 Port A/B Data Register
D.5.5 Port Data Direction Register
D-30
RESET:
MOTOROLA
DDQA7 DDQA6 DDQA5 DDQA4 DDQA3 DDQA2 DDQA1 DDQA0
PQA7
AN59
MULTIPLEXED ANALOG INPUTS:
15
15
U
EXTERNAL TRIGGER INPUTS:
ANALOG CHANNEL:
0
RESET:
MULTIPLEXED ADDRESS OUTPUTS:
Only the upper six bits of IVB[7:0] can be initialized. During interrupt arbitration, the
vector provided by the QADC is made up of IVB[7:2], plus two low-order bits that
identify one of the four QADC interrupt sources. Once IVB is written, the two low-order
bits always read as zeros.
QADC ports A and B are accessed through two 8-bit port data registers (PORTQA and
PORTQB). Port A pins are referred to as PQA[7:0] when used as an 8-bit input/output
port. Port A can also be used for analog inputs (AN[59:52]), external trigger inputs
(ETRIG[2:1]), and external multiplexer address outputs (MA[2:0]).
Port B pins are referred to as PQB[7:0] when used as an 8-bit input only port. Port B
can also be used for non-multiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy,
ANx, ANw) analog inputs.
Bits in this register control the direction of the port QA pin drivers when pins are con-
figured for I/O. Setting a bit configures the corresponding pin as an output; clearing a
bit configures the corresponding pin as an input. This register can be read or written
at any time.
PQA6
AN58
14
14
U
0
PQA5
AN57
13
13
U
0
ETRIG2 ETRIG1
PQA4
AN56
12
12
U
0
PQA3
AN55
11
11
0
U
PQA2
AN54
MA2
10
10
0
U
REGISTER SUMMARY
PQA1
AN53
MA1
9
0
U
9
PQA0
AN52
MA0
8
0
U
8
PQB7
AN51
7
0
U
7
PQB6
AN50
6
0
U
6
PQB5
AN49
5
0
U
5
PQB4
AN48
RESERVED
4
0
U
4
PQB3
AN3
ANz
U
3
0
3
PQB2
USER’S MANUAL
AN2
ANy
U
2
0
2
MC68336/376
$YFF206
$YFF207
$YFF208
PQB1
AN1
ANx
U
1
0
1
PQB0
ANw
AN0
U
0
0
0