MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 350

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

QACR1 — Control Register 1
CIE1 — Queue 1 Completion Interrupt Enable
PIE1 — Queue 1 Pause Interrupt Enable
SSE1 — Queue 1 Single-Scan Enable
MQ1[2:0] — Queue 1 Operating Mode
D-32
RESET:
MOTOROLA
CIE1
15
0
CIE1 enables completion interrupts for queue 1. The interrupt request is generated
when the conversion is complete for the last CCW in queue 1.
PIE1 enables pause interrupts for queue 1. The interrupt request is generated when
the conversion is complete for a CCW that has the pause bit set.
SSE1 enables a single-scan of queue 1 after a trigger event occurs. The SSE1 bit may
be set to a one during the same write cycle that sets the MQ1[2:0] bits for the single-
scan queue operating mode. The single-scan enable bit can be written as a one or a
zero, but is always read as a zero.
The SSE1 bit allows a trigger event to initiate queue execution for any single-scan op-
eration on queue 1. The QADC clears SSE1 when the single-scan is complete.
The MQ1 field selects the queue operating mode for queue 1. Table D-25 shows the
different queue 1 operating modes.
0 = Queue 1 completion interrupts disabled.
1 = Generate an interrupt request after completing the last CCW in queue 1.
0 = Queue 1 pause interrupts disabled.
1 = Generate an interrupt request after completing a CCW in queue 1 which has
PIE1
14
0
the pause bit set.
SSE1
13
0
MQ1[2:0]
000
001
010
011
100
101
110
111
12
NOT USED
Table D-25 Queue 1 Operating Modes
11
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE1)
External trigger rising edge single-scan mode (on ETRIG1 pin)
External trigger falling edge single-scan mode (on ETRIG1 pin)
Reserved mode, conversions do not occur
Software triggered continuous-scan mode (started with SSE1)
External trigger rising edge continuous-scan mode (on ETRIG1 pin)
External trigger falling edge continuous-scan mode (on ETRIG1 pin)
10
0
MQ1[2:0]
REGISTER SUMMARY
9
0
8
0
Queue 1 Operating Mode
7
6
5
RESERVED
4
3
USER’S MANUAL
2
MC68336/376
$YFF20C
1
0