HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 10

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
iv
6.1.3
6.1.4
Register Descriptions......................................................................................................... 134
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Overview of Bus Control................................................................................................... 142
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Basic Bus Interface............................................................................................................ 148
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
Burst ROM Interface ......................................................................................................... 161
6.5.1
6.5.2
6.5.3
Idle Cycle........................................................................................................................... 164
6.6.1
6.6.2
Bus Release........................................................................................................................ 167
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
Bus Arbitration .................................................................................................................. 170
6.8.1
6.8.2
6.8.3
6.8.4
Resets and the Bus Controller............................................................................................ 171
Pin Configuration ................................................................................................. 133
Register Configuration ......................................................................................... 133
Bus Width Control Register (ABWCR) ............................................................... 134
Access State Control Register (ASTCR).............................................................. 135
Wait Control Registers H and L (WCRH, WCRL).............................................. 136
Bus Control Register H (BCRH).......................................................................... 139
Bus Control Register L (BCRL)........................................................................... 141
Area Partitioning .................................................................................................. 142
Bus Specifications ................................................................................................ 144
Memory Interfaces................................................................................................ 145
Advanced Mode.................................................................................................... 145
Areas in Normal Mode (ZTAT, Mask ROM, and No On-Chip ROM
Versions Only)...................................................................................................... 146
Chip Select Signals............................................................................................... 147
Overview .............................................................................................................. 148
Data Size and Data Alignment ............................................................................. 148
Valid Strobes ........................................................................................................ 150
Basic Timing ........................................................................................................ 151
Wait Control ......................................................................................................... 159
Overview .............................................................................................................. 161
Basic Timing ........................................................................................................ 161
Wait Control ......................................................................................................... 163
Operation .............................................................................................................. 164
Pin States in Idle Cycle ........................................................................................ 167
Overview .............................................................................................................. 167
Operation .............................................................................................................. 167
Pin States in External Bus Released State............................................................ 168
Transition Timing................................................................................................. 169
Usage Note ........................................................................................................... 170
Overview .............................................................................................................. 170
Operation .............................................................................................................. 170
Bus Transfer Timing ............................................................................................ 171
External Bus Release Usage Note ........................................................................ 171