HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 901

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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Table D.1
Port Name
Pin Name
PG
PG
PG
IRQ7
PG
IRQ6
Legend:
H
L
T
kept
DDR
OPE
WAITE
BRLE
Note: * Indicates the state after completion of the executing bus cycle.
3
2
1
0
/CS1
/CS2
/CS3/
/ADTRG/ 1 to 3, 7
: High level
: Low level
: High impedance
: Input port becomes high-impedance, output port retains state
: Data direction register
: Output port enable
: Wait input enable
: Bus release enable
I/O Port States in Each Processing State (cont)
MCU
Operating
Mode
1 to 3, 7
4 to 6
4 to 6
Power-
On
Reset
T
T
T
T
Manual
Reset
kept
[DDR = 0]
T
[DDR = 1]
H*
kept
kept
Hardware
Standby
Mode
T
T
T
T
Software
Standby
Mode
kept
[DDR · OPE = 0]
T
[DDR · OPE = 1]
H
kept
kept
Bus
Release
State
kept
T
kept
T
Program
Execution
State
Sleep Mode
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS
I/O port
I/O port
1
to CS
891
3

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