HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 305

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both
edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
0
1
Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is
Bits 2, 1, and 0—Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT
counter clock. The clock source can be selected independently for each channel. Table 9.4 shows
the clock sources that can be set for each channel.
Table 9.4
Channel
0
1
2
3
4
5
Legend
Blank : No setting
288
ignored if the input clock is ø/1, or when overflow/underflow of another channel is selected.
: Setting
ø/1
Bit 3
CKEG0
0
1
—
TPU Clock Sources
ø/4
ø/16 ø/64 ø/256 ø/1024 ø/4096
Internal Clock
Description
Count at rising edge
Count at falling edge
Count at both edges
TCLKA TCLKB TCLKC TCLKD Channel
External Clock
(Initial value)
Overflow/
Underflow
on Another