HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 4

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Page
160
273
294 to 309 9.2.3 Timer I/O Control Register (TIOR)
420
429 to 431 Table 12.3 BRR Settings for Various Bit
441
461
467
478, 479
481
483
484
488, 489
491 to 493 13.3.6
497, 498
510
519 to 524 14.6 Usage Notes
529
532
Item
Figure 6.14 Example of Wait Insertion
Timing
8.12.2 Register Configuration, Port G
Data Direction Register (PGDDR)
12.2.5 Serial Mode Register (SMR)
Rates (Asynchronous Mode)
Figure 12.2 Data Format in Asynchronous
Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
Figure 12.15 Sample SCI Initialization
Flowchart
Figure 12.20 Sample Flowchart of
Simultaneous Serial Transmit and Receive
Operations
13.2.2 Serial Status Register (SSR)
13.2.4 Serial Control Register (SCR)
Figure 13.2 Schematic Diagram of Smart
Card Interface Pin Connections
Figure 13.3 Smart Card Interface Data
Format
Table 13.5 Examples of Bit Rate B (bit/s)
for Various BRR Settings (When n = 0)
Table 13.6 Examples of BRR Settings for
Bit Rate B (bit/s) (When n = 0)
Data Transmission
13.3.7
14.2.3
15.2.2 D/A Control Register (DACR)
15.4 Usage Notes
Data Transfer Operations, Serial
Operation in GSM Mode
A/D Control Register (ADCR)
Revision
Amended
Description amended
Amended (Register name added to tables)
Description of bit 3 amended
Amendments to some Error column
entries (values not entered for error of 3%
or above)
Amended
Note added
Note amended
Description of bits 4 and 2 amended
Description of bits 1 and 0 amended
Amended
Amended
Amended (ø = 20.00 MHz column added)
Amended
Amended (Old section 13.3.7, Example of
Use in Software Standby Mode, replaced
with new section)
Description of bits 7 and 6 amended
(1) Amendment of setting range for analog
(2) Deletion of module stop mode
Bit 5 description amended
New
power supply pins etc.
interrupts