HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 377

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

9.7
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.48 shows the input clock
conditions in phase counting mode.
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches the TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
Where
360
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes: Phase difference and overlap
Figure 9.48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
f =
Usage Notes
f
ø : Operating frequency
N : TGR set value
Pulse width
(N + 1)
: Counter frequency
Overlap
Pulse width
Phase
differ-
ence
Overlap
: 1.5 states or more
: 2.5 states or more
Phase
differ-
ence
Pulse width
Pulse width
Pulse width