HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 393

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 2
CKS2
0
1
Note: * If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
10.2.5
TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and
control compare match output.
TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.
Bit
Initial value
R/W
TCSR0
TCSR1
Bit
Initial value
R/W
TCNT0 compare match signal, no incrementing clock is generated. Do not use this setting.
Note: *
Bit 1
CKS1
0
1
0
1
Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)
Only 0 can be written to bits 7 to 5, to clear these flags.
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Bit 0
CKS0
0
1
0
1
0
1
0
1
R/(W)*
R/(W)*
CMFB
CMFB
7
0
7
0
Description
Clock input disabled
Internal clock, counted at falling edge of ø/8
Internal clock, counted at falling edge of ø/64
Internal clock, counted at falling edge of ø/8192
For channel 0: count at TCNT1 overflow signal*
For channel 1: count at TCNT0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
R/(W)*
R/(W)*
CMFA
CMFA
6
0
6
0
R/(W)*
R/(W)*
OVF
OVF
5
0
5
0
ADTE
R/W
—
—
4
0
4
1
OS3
OS3
R/W
R/W
3
0
3
0
OS2
OS2
R/W
R/W
2
0
2
0
OS1
R/W
OS1
R/W
1
0
1
0
OS0
OS0
R/W
R/W
(Initial value)
0
0
0
0
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