HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 654

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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Table 20.7 Timing of On-Chip Supporting Modules (cont)
Condition A: —In planning stage—
Condition B: V
Item
SCI
A/D
converter
Input
clock
cycle
Input clock pulse
width
Input clock rise
time
Input clock fall
time
Transmit data
delay time
Receive data setup
time (synchronous)
Receive data hold
time (synchronous)
Trigger input setup
time
V
ø = 2 to 10 MHz, T
T
ø = 2 to 20 MHz, T
T
a
a
CC
CC
= –40 to +85 C (wide-range specifications)
= –40 to +85 C (wide-range specifications)
= AV
= AV
Asynchro-
nous
Synchro-
nous
CC
CC
= 3.0 V to 5.5 V, V
= 5.0 V 10%, V
Symbol
t
t
t
t
t
t
t
t
Scyc
SCKW
SCKr
SCKf
TXD
RXS
RXH
TRGS
a
a
= –20 to +75 C (regular specifications),
= –20 to +75 C (regular specifications),
Min
4
6
0.4
100
100
50
Condition A
ref
ref
= 4.5 V to AV
= 3.0 V to AV
Max
0.6
1.5
1.5
100
Min
4
6
0.4
50
50
30
Condition B
CC
CC
, V
, V
Max
0.6
1.5
1.5
50
SS
SS
= AV
= AV
Unit
t
t
t
ns
ns
ns
ns
SS
cyc
Scyc
cyc
SS
= 0 V,
= 0 V,
Test Conditions
Figure 20.24
Figure 20.25
Figure 20.26
645

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