HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 226

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.2.2
Table 8.2 shows the port 1 register configuration.
Table 8.2
Name
Port 1 data direction register
Port 1 data register
Port 1 register
Note: * Lower 16 bits of the address.
Port 1 Data Direction Register (P1DDR)
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the TPU is initialized by a
manual reset, the pin states are determined by the P1DDR and P1DR specifications.
Whether the address output pins maintain their output state or go to the high-impedance state in a
transition to software standby mode is selected by the OPE bit in SBYCR.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Bit
Initial value
R/W
Modes 1 to 3 and 7*
The corresponding port 1 pins are output ports when P1DDR is set to 1, and input ports when
cleared to 0.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
Register Configuration
Port 1 Registers
:
:
:
P17DDR
W
7
0
P16DDR
W
6
0
Abbreviation
P1DDR
P1DR
PORT1
P15DDR
W
5
0
P14DDR
W
4
0
R/W
W
R/W
R
P13DDR
W
3
0
Initial Value
H'00
H'00
Undefined
P12DDR
W
2
0
P11DDR
W
1
0
Address*
H'FEB0
H'FF60
H'FF50
P10DDR
W
0
0
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