HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 433

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In clocked synchronous mode,
parity bit addition and checking is not performed, regardless of the PE bit setting.
Bit 5
PE
0
1
Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and
when parity addition and checking is disabled in asynchronous mode.
Bit 4
O/E
0
1
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/E bit.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Description
Even parity*
Odd parity*
2
1
(Initial value)
(Initial value)
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