HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 413

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

11.2
11.2.1
TCNT is an 8-bit readable/writable *
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) *
interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: 1. The method for writing to TCNT is different from that for general registers to prevent
11.2.2
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * The method for writing to TCSR is different from that for general registers to prevent
398
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Can only be written with 0 for flag clearing.
2. The WDTOVF pin function is not supported by the F-ZTAT version.
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
Register Descriptions
Timer Counter (TCNT)
Timer Control/Status Register (TCSR)
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
:
:
:
:
:
:
R/(W)*
OVF
R/W
7
0
7
0
WT/IT
R/W
R/W
6
0
6
0
1
up-counter.
TME
R/W
R/W
5
0
5
0
R/W
—
—
4
0
4
1
R/W
—
—
3
0
3
1
CKS2
R/W
R/W
2
0
2
0
2
or an interval timer
CKS1
R/W
R/W
1
0
1
0
CKS0
R/W
R/W
0
0
0
0