HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 462

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

448
Serial data reception (asynchronous mode)
Figure 12.7 shows a sample flowchart for serial reception.
The following procedure should be used for serial data reception.
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Read ORER, PER, and
PER FER ORER= 1
All data received?
FER flags in SSR
Figure 12.7 Sample Serial Reception Data Flowchart
Start reception
Initialization
RDRF= 1
<End>
Yes
Yes
No
(Continued on next page)
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1]
[2] [3]
[4]
[5]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
processing, ensure that the
ORER, PER, and FER flags are
all cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC is activated by an
RXI interrupt and the RDR value
is read.
Receive error processing and