HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 159

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
0
1
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM
interface. In normal mode*, the selection can be made from the entire external space .
Burst ROM interface and PSRAM burst operation cannot be set at the same time.
Note: * ZTAT, mask ROM, and ROMless versions only.
Bit 5
BRSTRM
0
1
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
0
1
140
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
Description
Area 0 is basic bus interface
Area 0 is burst ROM interface
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
(Initial value)
(Initial value)
(Initial value)
(Initial value)