HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 391

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

10.2.3
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a
single 16-bit register so they can be accessed together by word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag of TCSR is set. Note, however, that comparison is disabled during the
T2 state of a TCOR write cycle.
The timer output can be freely controlled by these compare match signals and the settings of
output select bits OS3 and OS2 of TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
10.2.4
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at
which TCNT is cleared, and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 10.3, Operation.
Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt
requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1.
Bit 7
CMIEB
0
1
Bit
Initial value
R/W
Bit
Initial value
R/W
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
Time Control Registers 0 and 1 (TCR0, TCR1)
Description
CMFB interrupt requests (CMIB) are disabled
CMFB interrupt requests (CMIB) are enabled
:
:
:
:
:
:
R/W
15
1
CMIEB
R/W
7
0
R/W
14
1
R/W
13
1
CMIEA
R/W
6
0
R/W
TCORB0
12
1
R/W
11
1
OVIE
R/W
5
0
R/W
10
1
R/W
9
1
CCLR1
R/W
4
0
R/W
8
1
R/W
CCLR0
7
1
R/W
3
0
R/W
6
1
R/W
5
1
CKS2
R/W
2
0
R/W
TCORB1
4
1
R/W
3
1
CKS1
R/W
1
0
R/W
2
1
(Initial value)
R/W
1
1
CKS0
R/W
0
0
R/W
0
1
375