HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 400

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HD6412340

Manufacturer Part Number
HD6412340
Description
H8S/2345 F-ZTAT Hardware Manual
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet

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10.3.3
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10.7
shows the timing of this operation.
10.3.4
The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
10.8 shows the timing of this operation.
384
ø
External reset
input pin
Clear signal
TCNT
Timing of External RESET on TCNT
Timing of Overflow Flag (OVF) Setting
ø
TCNT
Overflow signal
OVF
Figure 10.7 Timing of External Reset
Figure 10.8 Timing of OVF Setting
N–1
H'FF
N
H'00
H'00

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