HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 491

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

13.2
Registers added with the Smart Card interface and bits for which the function changes are
described here.
13.2.1
SCMR is an 8-bit readable/writable register that selects the Smart Card interface function.
SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode.
Bits 7 to 4—Reserved: Read-only bits, always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3
SDIR
0
1
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the SDIR bit for communication with an inverse convention card.
The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures,
see section 13.3.4, Register Settings.
Bit 2
SINV
0
1
Bit
Initial value
R/W
Register Descriptions
Smart Card Mode Register (SCMR)
Description
TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Description
TDR contents are transmitted as they are
Receive data is stored as it is in RDR
TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
:
:
:
—
—
7
1
—
—
6
1
—
—
5
1
—
—
4
1
SDIR
R/W
3
0
SINV
R/W
2
0
—
—
1
1
(Initial value)
(Initial value)
SMIF
R/W
0
0
477