HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 291

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

Port G Data Register (PGDR)
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG
PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port G Register (PORTG)
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin
states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset,
and in software standby mode.
274
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PG
0
).
:
:
:
:
:
:
Undefined
Undefined
—
—
—
—
7
7
Undefined
Undefined
—
—
—
—
6
6
4
to PG
Undefined
Undefined
4
—
—
—
—
5
5
to PG
0
) must always be performed on PGDR.
0
PG4DR
.
PG4
R/W
—*
R
4
0
4
PG3DR
PG3
R/W
—*
R
3
0
3
PG2DR
PG2
R/W
—*
R
2
0
2
PG1DR
R/W
PG1
—*
R
1
0
1
PG0DR
4
PG0
R/W
—*
to
R
0
0
0