HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 261

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

8.7.2
Table 8.11 shows the port B register configuration.
Table 8.11 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
244
Bit
Initial value
R/W
Modes 1, 4, and 5*
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Modes 2 and 6*
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while
clearing the bit to 0 makes the pin an input port.
Modes 3 and 7*
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
Register Configuration
:
:
:
PB7DDR
W
7
0
PB6DDR
W
6
0
PB5DDR
Abbreviation
PBDDR
PBDR
PORTB
PBPCR
W
5
0
PB4DDR
W
4
0
PB3DDR
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
PB2DDR
W
2
0
PB1DDR
W
1
0
Address *
H'FEBA
H'FF6A
H'FF5A
H'FF71
PB0DDR
W
0
0