HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 184

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 6.17 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
ø
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
Figure 6.17 Example of Idle Cycle Operation (2)
T
floating time
Long output
3
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
Data bus
HWR
RD
ø
T
(b) Idle cycle inserted
1
Bus cycle A
(Initial value ICIS1 = 1)
T
2
T
3
T
I
Bus cycle B
T
1
T
2
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