HD6412340 HITACHI [Hitachi Semiconductor], HD6412340 Datasheet - Page 842

• Manufacturer Part Number: HD6412340
• Description: H8S/2345 F-ZTAT Hardware Manual
• Manufacturer: HITACHI [Hitachi Semiconductor]

TCSR0—Timer Control/Status Register 0
TCSR1—Timer Control/Status Register 1
Note:
TCSR0
TCSR1
*
Only 0 can be written to bits 7 to 5, to clear these flags.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Compare Match Flag B
0
1
[Clearing condition]
• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB
• When the DTC is activated by a CMIB interrupt, while DISEL bit of MRB in DTC is 0.
[Setting condition]
Set when TCNT matches TCORB
:
:
:
:
:
:
R/(W)*
R/(W)*
CMFB
CMFB
Compare Match Flag A
7
0
7
0
0
1
[Clearing condition]
• Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA
• When the DTC is activated by a CMIA interrupt, while DISEL bit of MRB in DTC is 0.
[Setting condition]
Set when TCNT matches TCORA
R/(W)*
R/(W)*
CMFA
CMFA
Timer Overflow Flag
6
0
6
0
0
1
[Clearing condition]
• Cleared by reading OVF when OVF = 1, then writing 0 to OVF
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00)
R/(W)*
R/(W)*
OVF
OVF
5
0
5
0
A/D Trigger Enable (TCSR0 only)
0
1
A/D converter start requests by compare match A are disabled
A/D converter start requests by compare match A are enabled
ADTE
R/W
—
—
4
0
4
1
H'FFB2
H'FFB3
Output Select
0
1
OS3
OS3
R/W
R/W
3
0
3
0
0
1
0
1
No change when compare match B occurs
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B
occurs (toggle output)
Output Select
OS2
OS2
R/W
R/W
0
1
2
0
2
0
0
1
0
1
8-Bit Timer Channel 0
8-Bit Timer Channel 1
No change when compare
match A occurs
0 is output when compare
match A occurs
1 is output when compare
match A occurs
Output is inverted when
compare match A
occurs (toggle output)
OS1
R/W
OS1
R/W
1
0
1
0
OS0
OS0
R/W
R/W
0
0
0
0
833