MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 235
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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10.8 Functional Description
10.8.1 System Clock Modes
MMC2107 – Rev. 2.0
MOTOROLA
CAUTION:
This subsection provides a functional description of the clock module.
The system clock source is determined during reset. The value of
V
after reset is negated. If V
power-on reset, the internal clocks may glitch as the clock source is
changed between external clock mode and PLL clock mode. Whenever
V
Table 10-6
relationships for the possible clock modes.
XTAL must be tied low in external clock mode when reset is asserted. If
it is not, clocks could be suspended indefinitely.
The external clock is divided by two internally to produce the system
clocks.
1. f
DDSYN
DDSYN
Normal PLL clock mode
1:1 PLL clock mode
External clock mode
Freescale Semiconductor, Inc.
f
MFD ranges from 0 to 7.
RFD ranges from 0 to 7.
ref
sys
For More Information On This Product,
= input reference frequency
= CLKOUT frequency
is latched during reset and is expected to remain at that state
is changed in reset, an immediate loss of lock condition occurs.
Table 10-6. Clock-Out and Clock-In Relationships
Clock Mode
shows the clock-out frequency to clock-in frequency
Go to: www.freescale.com
Clock Module
DDSYN
is changed during a reset other than
f
f
f
sys
sys
sys
= f
= f
= f
ref
ref
ref
/2
(MFD + 2)/2
PLL Options
Functional Description
RFD
(1)
Technical Data
Clock Module
235
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