MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 457
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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Manufacturer
Quantity
Price
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AMD
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MMC2107CFCPV33
Manufacturer:
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20 000
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MMC2107 – Rev. 2.0
MOTOROLA
Q1
Q2
QS
Q1
Q2
QS
0000
IDLE
Q1:
IDLE
T1
0000
C1
IDLE
ACTIVE
TOR1
T1
1000
IDLE
Situation S3
the trigger overrun error status bit is set the same way, and that queue
execution continues unchanged.
The next two situations consider trigger events that occur for the lower
priority queue 2, while queue 1 is actively being serviced.
Situation S4
recognized while queue 1 is active is saved, and as soon as queue 1 is
finished, queue 2 servicing begins.
C2
Freescale Semiconductor, Inc.
Figure 18-25. CCW Priority Situation 3
Figure 18-26. CCW Priority Situation 4
Q1:
PF1
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
T1
0100
C1
Q2:
1000
T2
(Figure
Go to: www.freescale.com
C2
PAUSE
Q2:
(Figure
ACTIVE
C1
TOR2
ACTIVE
T2
T2
0110
TRIGGERED
C3
C2
1011
PF2
18-25) shows that when the pause feature is in use,
18-26) shows that a queue 2 trigger event that is
C4
0101
CF1
T1
C1
C3
TOR1
ACTIVE
T1
1001
PAUSE
C2
ACTIVE
C4
0010
CF1
Queued Analog-to-Digital Converter (QADC)
C3
0001
C4
T2
CF2
IDLE
C3
TOR2
ACTIVE
T2
0010
IDLE
C4
CF2
IDLE
0000
IDLE
0000
Technical Data
Digital Control
457
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