MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 249
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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11.3 Signals
11.4 Memory Map and Registers
MMC2107 – Rev. 2.0
MOTOROLA
See
naming convention.
The ports programming model consists of these registers:
In emulation mode, accesses to the port registers are ignored and the
port access goes external so that emulation hardware can satisfy the
port access request. The cycle termination is always provided by the port
logic, even in emulation mode.
All port registers are word-, half-word, and byte-accessible and are
grouped to allow coherent access to port data register groups. Writing to
reserved bits in the port registers has no effect and reading returns 0s.
The I/O ports have a base address of 0x00c0_0000.
•
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Freescale Semiconductor, Inc.
Table 11-3
For More Information On This Product,
The port output data registers (PORTx) store the data to be driven
on the corresponding port pins when the pins are configured for
digital output.
The port data direction registers (DDRx) control the direction of
the port pin drivers when the pins are configured for digital I/O.
Port pin data/set data registers (PORTxP/SETx):
– Reflect the current state of the port pins
– Allow for setting individual bits in PORTx
The port clear output data registers (CLRx) allow for clearing
individual bits in PORTx.
The port pin assignment registers (PCDPAR and PEPAR) control
the function of each pin of the C, D, E, I7, and I6 ports.
Go to: www.freescale.com
in
Ports Module
11.5 Functional Description
for signal location and
Technical Data
Ports Module
Signals
249
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