MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 432

• Manufacturer Part Number: MMC2107CFCPV33
• Description: IC MCU 33MHZ 128K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2107CFCPV33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 0 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Analog-to-Digital Converter (QADC)
Technical Data
432
TOR2 — Queue 2 Trigger Overrun Flag
QS[9:6] — Queue Status Field
The software acknowledges that it has detected a trigger overrun
being set by writing a 0 to the trigger overrun, after the bit was read
as a 1. Once set, only software or reset can clear TOR1.
TOR2 indicates that an unexpected trigger event has occurred for
queue 2. TOR2 can be set when queue 2 is in the active, suspended,
and trigger pending states.
The TOR2 trigger overrun can occur only when using an external
trigger mode or a periodic/interval timer mode. Trigger overruns
cannot occur when the software-initiated single-scan mode and the
software-initiated continuous-scan mode are selected.
TOR2 occurs when a trigger event is received while queue 2 is
executing, suspended, or a trigger is pending. TOR2 has no effect on
the queue execution. A trigger event that causes a trigger overrun is
not retained since it is considered unexpected.
An unexpected trigger event may be a system overrun situation,
indicating a system loading mismatch. The software acknowledges
that it has detected a trigger overrun being set by writing a 0 to the
trigger overrun, after the bit was read as a 1. Once set, only software
or reset can clear TOR2.
The 4-bit read-only QS field indicates the current condition of queue 1
and queue 2. There are five queue status conditions:
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = At least one unexpected queue 1 trigger event has occurred or
0 = No unexpected queue 1 trigger events have occurred
1 = At least one unexpected queue 2 trigger event has occurred.
0 = No unexpected queue 2 trigger events have occurred.
– Idle
– Active
– Paused
– Suspended
– Trigger pending
queue 1 reaches an end-of-queue condition for the second
time in gated mode
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA