MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 569
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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MMC2107 – Rev. 2.0
MOTOROLA
SWO — Software Debug Occurrence Flag
TO — Trace Count Occurrence Flag
FRZO — FIFO Freeze Occurrence Flag
SQB — Sequential Breakpoint B Arm Occurrence Flag
SQA — Sequential Breakpoint A Arm Occurrence Flag
PM1 and PM0 — Processor Mode Field
SWO bit is set when the processor enters debug mode of operation
as a result of the execution of the BKPT instruction. This bit is cleared
on test logic reset or when debug mode is exited with the GO and EX
bits set.
TO is set when the trace counter reaches zero with the trace mode
enabled and the CPU enters debug mode. This bit is cleared on test
logic reset or when debug mode is exited with the GO and EX bits set.
FRZO is set when a FIFO freeze occurs. This bit is cleared on test
logic reset or when debug mode is exited with the GO and EX bits set.
SQB is set when sequential operation is enabled and a memory
breakpoint B event has occurred to enable trace counter operation.
This bit is cleared on test logic reset or when debug mode is exited
with the GO and EX bits set.
SQA is set when sequential operation is enabled and a memory
breakpoint A event has occurred to enable memory breakpoint B
operation. This bit is cleared on test logic reset or when debug mode
is exited with the GO and EX bits set.
These flags reflect the processor operating mode. They allow
coordination of the OnCE controller with the CPU for synchronization.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
and PM0
PM1
Go to: www.freescale.com
Table 21-7. Processor Mode Field Settings
00
01
10
11
Processor in normal mode
Processor in stop, doze, or wait mode
Processor in debug mode
Reserved
Meaning
JTAG Test Access Port and OnCE
Functional Description
Technical Data
569
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