MMC2107CFCPV33 Freescale Semiconductor, MMC2107CFCPV33 Datasheet - Page 408
MMC2107CFCPV33
Manufacturer Part Number
MMC2107CFCPV33
Description
IC MCU 33MHZ 128K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheet
1.MMC2107CFCAF33.pdf
(618 pages)
Specifications of MMC2107CFCPV33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
0 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Queued Analog-to-Digital Converter (QADC)
18.6.3 External Trigger Input Pins
18.6.4 Multiplexed Address Output Pins
Technical Data
408
Since port QB pins are input only, a data direction register is not
necessary. The digital input signal states are read by the software in the
lower half of the port data register.
The QADC uses two external trigger pins (ETRIG[2:1]). Each of the two
input external trigger pins is associated with one of the scan queues,
queue 1 or queue 2. The assignment of ETRIG[2:1] to a queue is made
in QACR0 by the TRG bit. When TRG = 0, ETRIG1 triggers queue 1 and
ETRIG2 triggers queue 2. When TRG = 1, ETRIG1 triggers queue 2 and
ETRIG2 triggers queue 1.
In the non-multiplexed mode, the eight channel pins are connected to an
internal multiplexer which routes the analog signals into the internal A/D
converter.
In the externally multiplexed mode, the QADC allows automatic channel
selection through up to four external 4-to-1 selector chips. The QADC
provides a 2-bit multiplexed address output to the external multiplex
chips to allow selection of one of four inputs. The multiplexed address
output signals (MA[1:0]) can be used as multiplexed address output bits
or as general-purpose I/O.
MA[1:0] are used as the address inputs for one to two dual 4-channel
multiplexer chips. Since the MA[1:0] pins are digital outputs in the
multiplexed mode, the software programmed input/output direction for
the multiplexed address pins in the data direction register is superseded.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA
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