s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 165

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
LD —
LD
Operation:
Description:
Load
dst,src
The contents of the source are loaded into the destination. The source's contents are unaffected.
If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two times
in succession, only the first LD will be executed; the other similar instructions that immediately
follow the first LD will be treated like a NOP. This is called the 'redundancy effect' (see examples
below).
Operand
RR,#imm
Operand
A,@RRa
EA,@HL
@HL,EA
A,@RRa
EA,RRb
RRb,EA
@HL,A
Ra,#im
EA,DA
DA,EA
Ra,#im
A,#im
A,#im
A,DA
DA,A
A,Ra
Ra,A
A,DA
A,Ra
Load 4-bit immediate data to A
Load indirect data memory contents to A
Load direct data memory contents to A
Load register contents to A
Load 4-bit immediate data to register
Load 8-bit immediate data to register
Load contents of A to direct data memory
Load contents of A to register
Load indirect data memory contents to EA
Load direct data memory contents to EA
Load register contents to EA
Load contents of A to indirect data memory
Load contents of EA to data memory
Load contents of EA to register
Load contents of EA to indirect data memory
a7
d3
1
1
1
1
0
1
a6
d2
0
0
0
1
0
1
a5
d1
1
0
0
0
0
0
Binary Code
Operation Summary
a4
d0
1
0
0
1
0
1
d3
a3
1
1
1
1
1
1
d2
a2
i2
r2
r2
1
1
0
d1
a1
i1
r1
r1
0
0
0
d0
a0
i0
r0
r0
0
1
1
A
A
A
A
Ra
im
(RRa)
DA
Ra
im
Operation Notation
SAM47 INSTRUCTION SET
Bytes
1
1
2
2
2
2
2
2
2
2
2
1
2
2
2
Cycles
1
1
2
2
2
2
2
2
2
2
2
1
2
2
2
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