s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 297

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
TIMERS and TIMER/COUNTERS
TC1B PROGRAMMABLE TIMER/COUNTER FUNCTION
Timer/counter 1B can be programmed to generate interrupt requests at variable intervals, based on the system clock
frequency you select. The 8-bit TC1B mode register, TMOD1B, is used to activate the timer/counter and to select
the clock frequency; the 8-bit reference register, TREF1B, is used to store the value for the desired number of clock
pulses between interrupt requests. The 8-bit counter register, TCNT1B, counts the incoming clock pulses, which are
compared to the TREF1B value. When there is a match, an interrupt request is generated.
To program timer/counter 1B to generate interrupt requests at specific intervals, select one of the four internal clock
frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF1B register.
TCNT1B is incremented each time an internal counter pulse is detected with the reference clock frequency specified
by TMOD1B.4–TMOD1B.6 settings. To generate an interrupt request, the TC1B interrupt request flag (IRQT2) is set
to logic one, the status of TOL2 is inverted, and the interrupt is output. The content of TCNT1B is then cleared to
00H, and TC1B continues counting. The interrupt request mechanism for TC1B includes an interrupt enable flag
(IET2) and an interrupt request flag (IRQT2).
TC1B TIMER/COUNTER OPERATION SEQUENCE
The general sequence of operations for using TC1B can be summarized as follows:
1. Set TMOD1B.7 to "0" to be operated as timer/counter 1A, 1B.
2. Set TMOD1B.2 to "1" to enable TC1B.
3. Set TMOD1B.6 to "1" to enable the system clock (fxx) input.
4. Set TMOD1B.5 and TMOD1B.4 bits to desired internal frequency (fxx/2 n ).
5. Load a value to TREF1B to specify the interval between interrupt requests.
6. Set the TC1B interrupt enable flag (IET2) to "1".
7. Set TMOD1B.3 bit to "1" to clear TCNT1B, IRQT2, and TOL2, and start counting.
8. TCNT1B increments with each internal clock pulse.
9. When the comparator shows TCNT1B = TREF1B, the IRQT2 flag is set to "1" and an interrupt request is
generated.
10. Output latch (TOL2) logic toggles high or low.
11. TCNT1B is cleared to 00H and counting resumes.
12. Programmable timer/counter operation continues until TMOD1B.2 is cleared to "0".
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