s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 235

• Manufacturer Part Number: s3c72m9
• Description: The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
• Manufacturer: Samsung Semiconductor, Inc.

RESET
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
9
RESET
OVERVIEW
When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is initiated
and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has
elapsed, normal system operation resumes.
Regardless of when the RESET occurs — during normal operating mode or during a power-down mode — most
hardware register values are set to the reset values described in Table 9-1 below. The current status of several
register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs
during normal operating mode, their values are undefined. Current values that are retained in this case are as follows:
— Carry flag
— Data memory values
— General-purpose registers E, A, L, H, X, W, Z, and Y
— Serial I/O buffer register (SBUF)
Oscillator
Stabilization Wait Time
(31.3 ms/4.19 MHz)
RESET
Input
Normal Mode or
Operatng Mode
Idle Mode
Power-down
Mode
RESET Operation
Figure 9-1. Timing for Oscillation Stabilization After RESET
9-1